Three research teams from the Integrated Circuits and Systems Laboratory (ICSL) led by Professor Jaehyuck Choi received top honors at the 26th Korea Semiconductor Design Challenge. The team composed of researchers Jeongbeom Seo, Yuhwan Shin, Junseok Lee and Joohan Lee won the 추천, while the teams of Munjae Chae, Seheon Jang, Seungjae Lee and Sarang Lee, and Jaeho Kim, Myeongho Han, Hyunjun Song and Seohyeon Kwak each received Corporate Special Awards sponsored by MathWorks Korea and SK hynix, respectively.

추천: Ultra-low-power quadrature clock generation and distribution technology with jitter filtering and instantaneous toggling functionality for next-generation High Bandwidth Memory (HBM) semiconductor applications

추천 (MathWorks Korea): A 65fsrms-Jitter and-272dB-FoM_jitter,N, Fractional-N Digital PLL with a Quantization–Error-Compensating BBPD and an Orthogonal-Polynomial LMS Calibration

추천 (SK hynix): High-speed, command-aware hybrid voltage regulator with minimized voltage drop for next-generation HBM semiconductor applications

Source:/추천/news?md=v&bbsidx=56976

Translated by: Changhoon Kang, English Editor of the Department of Electrical and Computer Engineering, changhoon27@snu.ac.kr